1. Field of the Invention
The invention relates to methods for producing a semiconductor wafer having a front side coated by chemical vapor deposition (CVD).
2. Background Art
During chemical vapor deposition, in particular during the deposition of an epitaxial layer on a polished semiconductor wafer, inter alia, two phenomena may occur which are known by the terms “autodoping” and “halo”.
In “autodoping” dopants pass from the rear side of the semiconductor wafer via the gas phase into the deposition gas, which is fed over the front side of the semiconductor wafer. They are then incorporated into the epitaxial layer, predominantly in the edge region of the front side of the semiconductor wafer, and therefore cause more or less pronounced undesired radial fluctuation in the resistivity of the epitaxial layer.
“Halo” denotes a scattered light effect which is caused by light-scattering structures on the rear side of the semiconductor wafer which becomes apparent when a collimated light beam is shone onto the rear side of the semiconductor wafer. The structures mark transitions on the surface of the rear side of the semiconductor wafer, at which regions with a native oxide layer adjoin regions where such an oxide layer has not been or is no longer present. These transitions occur when removal of the native oxide layer during the pretreatment in a hydrogen atmosphere (“pre-bake”) was incomplete before the actual epitaxial deposition. One means of quantifying this effect consists of a scattered-light measurement of the haze (turbidity, opacity), for example with an SP1 light scattering meter from KLA Tencor, in the so-called DNN (“DarkField Narrow Normal”) or DWN (“DarkField Wide Normal”) channel.
In order to avoid problems with “autodoping” U.S. Pat. No. 6,129,047 proposes providing slits in the bottom of the susceptor's depression (“pocket”) holding the semiconductor wafer, wherein the slits are arranged on the outer edge of the bottom of the susceptor. Dopants defusing out from the rear side of the semiconductor wafer can be removed from the reactor without reaching the front side of the semiconductor wafer, by a purging gas fed through slits in the susceptor onto the wafer rear side.
According to U.S. Pat. No. 6,596,095 B2, there are small holes in the entire bottom of the susceptor for the same purpose. Here, too, the dopant diffusing out from the rear side of the semiconductor wafer is transported away by guiding a purging gas past the wafer. These measures are also effective against “halo” formation because they facilitate removal of the native oxide layer, since gaseous reaction products that arise when the native oxide is dissolved are likewise transported away through the holes in the bottom and the purging gas flowing past.
DE 10328842 discloses a susceptor having a gas-permeable structure with a porosity of at least 15% and a density of 0.5 to 1.5 g/cm3. By using such a porous susceptor, the gaseous reaction products which are formed during the pretreatment when the native oxide layer is dissolved, and also dopants diffusing from the semiconductor wafer to be coated, can escape through the pores of the susceptor to the rear side of the susceptor, and be taken up by means of a purging gas flow and removed from the reactor. Using the susceptor therein described also avoids undesired nanotopography effects on the rear side of the semiconductor wafer, which occur in the case of susceptors with holes. Holes in the susceptor influence the temperature field on the front side and rear side of the semiconductor wafer to be coated, which leads to locally different deposition rates and thus to said nanotopography effects. The term nanotopography denotes height fluctuations in the nanometer range, which are measured over a lateral extent of 0.5 mm to 10 mm.
A further problem in the epitaxy of semiconductor wafers involves stresses in the epitaxially coated semiconductor wafers, which can lead to dislocations and slips.
A number of methods for identifying slips in semiconductor wafers are known: on the one hand by visual inspection with collimated light by means of devices for inspecting the surface of semiconductors wafers, or else with devices which are suitable for determining the nanotopography.
The most sensitive method in this regard, however, is SIRD (“Scanning Infrared Depolarization”), since SIRD is able not only to detect slips but also able to measure photoelastic stresses. The SIRD method for identifying stress fields, slips, sliplines, epitaxial defects, which is based on inducing optical birefringence, is described for example in U.S. Pat. No. 6,825,487 B2.
Thermally induced stresses in epitaxially coated semiconductor wafers can be avoided if, during the epitaxy of semiconductor wafers, the temperatures are reduced during the pretreatment steps in a hydrogen atmosphere (bake) and with the addition of hydrogen chloride to the hydrogen atmosphere (HCl-etch) and also during the actual coating step. Lower coating temperatures, however, lead to an increased occurrence of undesired crystal defects such as stacking faults or typical epitaxial defects which are known by the terms “hillocks”, “mounds” or “pits”. At very low temperatures, polycrystalline growth may even occur. A further disadvantage is an impaired edge roll-off of the epitaxially coated layer and also a deterioration in the local flatness of the semiconductor wafer (geometry, SFQR). In addition, the growth rate decreases with lower deposition temperatures, which makes the process less economical.
Consequently, reducing the pretreatment and deposition temperatures is not acceptable at all, owing to the associated disadvantages.
In order to achieve good properties with regard to geometry for the epitaxial coating in single-wafer reactors (e.g. a Centura 300 mm reactor), it is absolutely necessary to move to high temperatures, since only then is the layer thickness distribution at the edge of the wafer suitable for obtaining or improving the initial geometry of the wafer.
At low temperatures the layer thickness in the vicinity of the edge of the wafer starts to fall and the initial geometry, which generally also already has a degree of edge roll-off, starts to deteriorate. At higher deposition temperatures, the epitaxial layer thickness exhibits a tendency to increase and this compensates for the edge roll-off of the substrate.
However, the stresses in the wafer increase greatly at higher deposition temperatures. This is due to the fact that dislocations arise and migrate more easily in the crystal since less activation energy is required for these processes at high temperatures. This in turn means that even in the case of small temperature differences between wafer and susceptor, the stresses are produced. This is associated with the fact that during coating, deposition gas also passes below the wafer and at some locations causes the wafer to grow on the susceptor. This effect is also called “bridging”. Such connecting bridges between susceptor and wafer form thermal bridges and—depending on whether the susceptor or the wafer is at a higher temperature—cause heat to be conducted into the wafer or withdrawn from the wafer. This heat flow in turn leads to stresses in the wafer.
US 2001/0037761 A1 discloses subjecting the susceptor with the semiconductor wafer lying thereupon to a thermal treatment in order to achieve intrinsic gettering properties in the bulk of the wafer. In this case, intrinsic gettering is made possible by oxygen precipitates. A crystal pulled by means of the CZ method and a wafer fabricated therefrom usually comprise oxygen in a concentration of 10 to 18 ppm. What can be achieved by thermal treatment and subsequent cooling is that the wafer comprises a region below its surface which is free of oxygen precipitates, while the bulk contains such oxygen precipitates (also called BMD=bulk micro defect) which act as intrinsic getters for metallic impurities.
In an epitaxy reactor, the semiconductor wafer is for this purpose firstly brought to a temperature of at least 1175° C., preferably to higher temperatures of up to 1300° C., held at this temperature for a few seconds (e.g. 12-15 s) and then cooled, e.g. at a cooling rate of 10-15° C./second. Higher cooling rates are possible if the semiconductor wafer is removed from the susceptor. Susceptors usually have one or more openings (the so-called lift pin holes) through which the semiconductor wafer can be raised by means of pins, so-called lift pins, while the susceptor remains in the original position. A result of lifting is that the semiconductor wafer is no longer in contact with the hot susceptor, which enables higher cooling rates of 25-30° C./second.
U.S. Pat. No. 5,198,071 proposes avoiding the “bridging” effect by the initial growth rate firstly being restricted to 0.1-1 μm/minute during the epitaxial deposition. However, such low growth rates make the process uneconomical. Moreover, it is proposed that bridging material between wafer and susceptor be removed by etching after epitaxial deposition and before the cooling process (that is to say, at deposition temperature). This has the disadvantage, however, that not only the connecting bridges between wafer and susceptor but also silicon material is etched away from the wafer rear side, which can lead to a deterioration in the overall geometry of the wafer. DE102005045338 discloses applying an elevation in the form of silicon material on the rear side of a silicon wafer, which elevation at least partly compensates for the edge roll-off brought about by the silicon wafer to be epitaxially coated. The height and extent of the application on the rear side of the silicon wafer can be set in a targeted manner by a suitable choice of the gas flows and the treatment durations. This is counteracted, however, by the etching away, as proposed in U.S. Pat. No. 5,198,071, of bridging material and rear side depositions.